1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a memory array of a nonvolatile ferroelectric memory.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 1 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 1, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
FIG. 2 is a block diagram showing the related art nonvolatile ferroelectric memory device having a cell structure of 1T/1C. As shown in FIG. 2, the related art nonvolatile ferroelectric memory device includes a main cell array 41, a reference cell array 42 assigned on a lower part of the main cell array 41, a wordline driver 43 formed at a side of the main cell array for applying a driving signal to the main cell array 41 and the reference cell array 42, and a sense amplifier unit 44 formed at a lower part of the reference cell array 42.
The wordline driver 43 applies the driving signal to a main wordline of the main cell array 41 and a reference wordline of the reference cell array 42. The sense amplifier unit 44 includes a plurality of sensing amplifiers and amplifies signals of a corresponding bitline B/L and bit bar line BB/L.
FIG. 3 is a partially detailed view of FIG. 2. As shown in the drawing, the main cell array has a folded bitline structure in the same manner as DRAM.
Also, the reference cell array 42 has a folded bitline structure and includes a reference cell wordline and reference cell plate line in pairs. At this time, reference cell wordline and the reference cell plate line pairs are defined as RWL_N-1 and RPL_N-1, and RWL_N and RPL_N, respectively.
When the main cell wordline MWL_N-1 and the main cell plate line MPL_N-1 are activated, the reference cell wordline RWL_N-1 and the reference cell plate line RPL_N-1 are activated. Therefore, data in the main cell is loaded into the bitline B/L and data in the reference cell is loaded into the bit bar line BB/L.
When the main cell wordline MWL_N and the main cell plate line MPL_N are activated, the reference cell wordline RWL_N and the reference cell plate line RPL_N are activated. Therefore, data in the main cell is loaded into the bit bar line BB/L and data in the reference cell is loaded into the bitline B/L.
The reference voltage REF by the reference cell exists between the bitline levels B_H (high) and B_L (low) by the main cell. To generate the reference voltage REF between the bitline levels B_H and B_L, the logic value "1" or "0" may be stored in a capacitor of the reference cell. When the logic value "1" is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is smaller than that of the capacitor of the main cell. When the logic value "0" is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is greater than that of the capacitor of the main cell. Thus, the related art nonvolatile ferroelectric memory can produce the reference voltage required by the sense amplifier unit 44 two ways.
A system of a sense amplifier unit in the related art ferroelectric memory will now be described. FIG. 4 is a circuit diagram illustrating one of the plurality of sensing amplifiers constituting the sense amplifier unit 44 of FIG. 3. As shown in FIG. 4, the related art sensing amplifier has a structure of a latch type sensing amplifier.
In other words, the sensing amplifier in FIG. 4 includes two PMOS transistors and two NMOS transistors, and these PMOS and NMOS transistors have latch type inverter structures. The first PMOS transistor MP1 and the second PMOS transistor MP2 face each other. An output terminal of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, and an output terminal of the second PMOS transistor MP2 is connected to a gate of the first PMOS transistor MP1. A SAP signal is commonly applied to input terminals of the first and second PMOS transistors MP1 and MP2. The SAP signal is an active signal that activates the first and second PMOS transistors MP1 and MP2.
The first NMOS transistor MN1 is connected to the output terminal of the first PMOS transistor MP1 in series. The second NMOS transistor MN2 is connected to the output terminal of the second NMOS transistor MN2 in series. The output terminal of the second NMOS transistor MN2 is connected to a gate of the first NMOS transistor MN1, and the output terminal of the first NMOS transistor MN1 is connected to a gate of the second NMOS transistor MN2.
A SAN signal is commonly applied to input terminals of the first and second NMOS transistors MN1 and MN2. The SAN signal is an active signal that activates the first and second NMOS transistors MN1 and MN2.
The output terminals of the first PMOS transistor MPI and first NMOS transistor MN1 are commonly connected to the bitline B_N. The output terminals of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the next bitline B_N+1.
The output of the sensing amplifier is respectively connected to the bitlines B_N and B_N+1 to be input and output to the main cell and the reference cell, respectively, thereby enabling input/output to the main cell and the reference cell.
The SAP signal, the SAN signal, and the signals of B_N and B_N+1 are all maintained at 1/2 Vcc for a precharged period when the sensing amplifier is not active. On the other hand, the SAP signal is pulled-up at high level and the SAN signal is pulled-down at low level.
A layout of a related art sense amplifier array will now be described. FIG. 5 illustrates a block of ferroelectric memory cells having a latch type sense amplifier employed therein. When the cell block has a system of an open bit line, the sensing amplifier is disposed between two cell array blocks 1 and 2 with two input terminals connected to respective bitlines for the cell array blocks 1 and 2.
As described above, the related art nonvolatile ferroelectric memory has various disadvantages. First, the use of different data buses in reading and writing data leads to a requirement for many data buses, which impedes an efficient reduced size layout design. Second, since an input terminal of the sensing amplifier is directly selectively connected to the upper and lower bitlines, loads between the bit line and the bit bar line may differ. Accordingly, since an amplification may occur in a state of different loads, the amplification may become unstable. Thus, the stability of amplification following read and write can not be expected. Third, the sense amplifier array provided in correspondence to the cell array block causes a limit in providing faster data input/output operations of the device because of bitline loading and difficulty in reducing a layout area for an entire chip array, which increases difficulty in an efficient disposal of cell arrays and sense amplifier arrays and leads to an increased time from memory design to mass production that reduces competitiveness of the product.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.